Sunday, 8 April 2012

VHDL Digital 8 - Bit Full ADDER Program


VHDL program for “8 Bit Adder” behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name:8 Bit Adder Design    
-- Module Name:BitAdder3 - Behavioral
-- Project Name:VHDL Program for "8 Bit Adder" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity BitAdder3 is
generic (N: natural :=2);
    Port ( X : in std_logic_vector(7 downto 0);
           Y : in std_logic_vector(7 downto 0);
           SUM : out std_logic_vector(7 downto 0);
           CARRY : out std_logic);
end BitAdder3;
architecture Behavioral of BitAdder3 is
signal result: std_logic_vector(8 downto 0);
begin
            result <= ('0' & X)+('0' & Y);
            SUM <= result(7 downto 0);
            CARRY <= result(8);
end Behavioral;

2 comments:

  1. The posts seems ENDEVOUR.....
    Thanks for the Information
    Regards
    Education Portal

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  2. Sir why can't we use + in full adder and half adder. I think we use this software to devlop ckt in logic gate form then where is logic gates in above program

    ReplyDelete