Sunday, 8 April 2012

VHDL Digital D - -Flip Flop Program


VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:00:36 04/01/12
-- Design Name: D FlipFlop Design  
-- Module Name: DFF1 - Behavioral
-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity DFF1 is
    Port ( D : in std_logic;
           CLK : in std_logic;
           Q : out std_logic;
           QN : out std_logic);
end DFF1;
architecture Behavioral of DFF1 is
begin
            process (CLK)
            begin
                        if CLK = '1' then
                        Q <= D;
                        QN <= NOT D;
                        end if;
            end process;
end Behavioral;

VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:08:41 04/01/12
-- Design Name: D FlipFlop Design  
-- Module Name: DLATCH2 - Behavioral
-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity DLATCH2 is
    Port ( DATAIN : in std_logic;
           ENABLE : in std_logic;
           DATAOUT : out std_logic);
end DLATCH2;
architecture Behavioral of DLATCH2 is
            begin
            process(DATAIN, ENABLE)
                        begin
                                    if (ENABLE='1') then
                                    DATAOUT <= DATAIN;
                        end if;
            end process;
end Behavioral;

VHDL program for “D – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:08:41 04/01/12
-- Design Name: D FlipFlop Design  
-- Module Name: DFLIPFLOP3 - Behavioral
-- Project Name:VHDL Program for "D FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity DFLIPFLOP3 is
    Port ( DATAIN : in std_logic;
           CLOCK : in std_logic;
           DATAOUT : out std_logic);
end DFLIPFLOP3;
architecture Behavioral of DFLIPFLOP3 is
begin
            process (DATAIN, CLOCK)
            begin
                        if (CLOCK = '1' and CLOCK'event) then
                        DATAOUT <= DATAIN;
                        end if;
            end process;
end Behavioral;

VHDL program for “D – Flip Flop With Clock and Reset Design” Behavioral design in Xilinx integrated software environment-
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 19:08:41 04/01/12
-- Design Name: D FlipFlop with Clock and Reset Design  
-- Module Name: DFLIPFLOP4 - Behavioral
-- Project Name:VHDL Program for "D FlipFlop with Clock and Reset Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity DFLIPFLOP4 is
    Port ( D : in std_logic;
           CLOCK : in std_logic;
           RESET : in std_logic;
           Q : out std_logic);
end DFLIPFLOP4;
architecture Behavioral of DFLIPFLOP4 is
begin
            process (CLOCK)
            begin
                        if (CLOCK'event and CLOCK='1')then
                        if RESET ='0' then
                        Q <= '0';
                        else
                        Q <= D;
                        end if;
                        end if;
            end process;
end Behavioral;




2 comments:

  1. I am extremely grateful to u for giving more valuable information..
    Thanks for the Information
    Regards
    Education Portal

    ReplyDelete
  2. boss while i am synthesizing the above programs there is a warning in synthesizing the ckt. can you please modify and reply me

    ReplyDelete