Monday, 9 April 2012

VHDL Digital DEC:BCD ENCODER Logic Program


VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment-
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-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 12:13:00 03/30/12
-- Design Name: Decimal to BCD Encoder Design    
-- Module Name: ENC3 - Behavioral
-- Project Name:VHDL Program for " Decimal to BCD Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
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entity ENC3 is
    Port ( Q : in std_logic;
           R : in std_logic;
           S : in std_logic;
           T : in std_logic;
           U : in std_logic;
           V : in std_logic;
           W : in std_logic;
           X : in std_logic;
           Y : in std_logic;
           Z : in std_logic;
           OUT0 : out std_logic;
           OUT1 : out std_logic;
           OUT2 : out std_logic;
           OUT3 : out std_logic);
end ENC3;
architecture Behavioral of ENC3 is
begin
            process (Q,R,S,T,U,V,W,X,Y,Z)
            begin
                        OUT0 <= R OR T OR V OR X OR Z;
                        OUT1 <= S OR T OR W OR X;
                        OUT2 <= U OR V OR W OR X;
                        OUT3 <= Y OR Z;
            end process;
end Behavioral;

1 comment:

  1. Nice post...helps to improve programing knowledge.........
    Thanks for the Information
    Regards
    Education Portal

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