Sunday, 8 April 2012

VHDL Digital SR - Flip Flop Program


VHDL program for “SR – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 11:35:16 04/02/12
-- Design Name: SR FlipFlop Design  
-- Module Name: SRFF1 - Behavioral
-- Project Name:VHDL Program for "SR FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity SRFF1 is
    Port ( S : in std_logic;
           R : in std_logic;
           Q : inout std_logic;
           QN : inout std_logic);
end SRFF1;
architecture Behavioral of SRFF1 is
begin
            process (S,R,Q,QN)
            begin
                        Q <= R NOR QN;
                        QN <= S NOR Q;
            end process;
end Behavioral;

VHDL program for “Clocked SR – Flip Flop Design” Behavioral design in Xilinx integrated software environment-
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 11:35:16 04/02/12
-- Design Name: Clocked SR FlipFlop Design  
-- Module Name: SRFF1 - Behavioral
-- Project Name:VHDL Program for "Clocked SR FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity SRFF1 is
    Port ( S : in std_logic;
           R : in std_logic;
           Q : inout std_logic;
           QN : inout std_logic);
end SRFF1;
architecture Behavioral of SRFF1 is
begin
            process (S,R,Q,QN)
            begin
                        Q <= R NOR QN;
                        QN <= S NOR Q;
            end process;
end Behavioral;
--------------------------------------------------------------------------------
-- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 11:35:16 04/02/12
-- Design Name: Clocked SR FlipFlop Design  
-- Module Name: SRFF2 - Behavioral
-- Project Name:VHDL Program for "Clocked SR FlipFlop Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------
entity SRFF2 is
    Port ( S : in std_logic;
           R : in std_logic;
           CLOCK : in std_logic;
           M : inout std_logic;
           N : inout std_logic;
           Q : inout std_logic;
           QN : inout std_logic);
end SRFF2;
architecture Behavioral of SRFF2 is
component SRFF1 is
            Port (S : in std_logic;
                     R : in std_logic;
                     Q : inout std_logic;
                      QN : inout std_logic);
end component;
begin
            M <= S AND CLOCK;
            N <= R AND CLOCK;
            a1: SRFF1 port map (M, N, Q, QN);
end Behavioral;

5 comments:

  1. helps to undersatnd clearly....it shows endevour..
    Thanks for the Information
    Regards
    Education Portal

    ReplyDelete
    Replies
    1. Hey would you please send the sr ff in following code.
      Dataflow
      Behavioral
      Structural.

      My id is: aalay011@gmail.com

      Delete
  2. SR Flip - Flop ที่มี S, R , Q , QN และ Clock เข้ามาเกี่ยวข้องด้วยอ่ะค่ะ จะสามารถเขียน VHDL CODE ไำด้ยังไงอ่ะค่ะ ??

    ReplyDelete
  3. hi would you please send the sr ff in following code.
    Dataflow
    Behavioral
    Structural.
    my mail id is: macherla.yamini@gmail.com?

    ReplyDelete